About this role
At Nokia of America, we're seeking a talented and motivated ASIC PD Coop to join our NI ON Comp R&D ASICs & Architecture 4B department. In this role, you'll be an integral part of our Physical Design sub-group, supporting various tasks that contribute to the successful tape-out of Nokia's ASICs. Your work will focus on applying data mining and analytics techniques to extract valuable insights from PPA metrics and physical design workflows, helping us optimize our designs and stay at the forefront of technology.
Number of Positions: 1
Duration: 4-8 months
Dates: Jan - May - August 2027
Location: Hybrid in San Jose, CA
EDUCATIONAL RECOMMENDATIONS:
Currently a candidate pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with an accredited university in the USA.
- Strong academic background with a passion for data analytics and automation.
- Experience with data mining and visualization tools is preferred.
- Familiarity with ASIC design and physical design workflows is an asset.
- Excellent problem-solving and analytical skills, with a keen eye for detail.
- Strong communication and collaboration skills, able to work effectively in a team environment.
- Ability to work independently and manage multiple tasks simultaneously.
- Proficiency in programming languages such as Python or C++ is advantageous.
- Knowledge of EDA tools and design methodologies is a plus.
- A self-starter with a proactive approach to learning and adapting to new technologies.