About this role
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
As a member of the CAD group, you will support the gate-level glitch noise and static timing analysis (STA) methodologies that ensure the signal integrity and robustness of Apple silicon across advanced technology nodes. In this role, you will learn and apply sign-off methodologies, margin models, and production CAD flows for crosstalk glitch and timing closure using industry-standard tools, under the guidance of senior engineers. You will work closely with CAD and physical design teams, assist with tool qualifications, help execute tapeout ECO tasks, and gain exposure to modern automation - including AI-agent workflows - used to scale analysis across our largest SOC designs.
In this role, your primary responsibilities will include:
Assist with applying established sign-off methodologies, noise margins, and tool qualification procedures for gate-level glitch noise and static timing analysis (STA), under senior engineer guidance.
Run and maintain existing production CAD flows and scripts for core noise and STA tools, supporting constraint setup through tapeout sign-off.
Help execute glitch noise analysis tasks - including checking glitch thresholds and propagation reports under supervision.
Assist with root-cause analysis of crosstalk glitch and timing anomalies, learning to use established automated triage workflows and AI-agent pipelines.
Work closely with design and physical design teams on noise/timing constraints and flow issues, escalating closure and waiver decisions to senior engineers.
Help execute noise and timing ECO tasks to support design convergence toward tapeout.
Participate in tool and version qualification activities, helping track QoR and performance data against golden baselines.
Help maintain documentation and learn noise and STA best practices from the team.
Minimum Qualifications
BS in Electrical Engineering, Computer Engineering, or related technical discipline.
Preferred Qualifications
1-2 years of experience in CAD methodology, EDA support, or digital design.
Foundational understanding of gate-level signal integrity concepts, including crosstalk glitch noise and static timing analysis (STA).
Exposure to industry-standard SI and STA tools (e.g., PrimeTime-SI, Tempus, or equivalent) through coursework, internship, or self-study.
Basic scripting skills in Python, Tcl, and/or Perl.
Willingness to learn noise and timing sign-off and ECO concepts with team support.
Ability to execute well-defined tasks with close guidance and mentorship.
Coursework or project exposure to standard cell library noise characterization (e.g., CCSN) or SPICE simulation basics.
Familiarity with place-and-route (P&R) concepts and physical design flow basics.
Curiosity about AI/LLM-assisted workflows for CAD scripting, report parsing, or automated triage.
Good communication skills and eagerness to learn.